Bidirectional zener diode and method for manufacturing bidirectional zener diode

ABSTRACT

A bidirectional Zener diode includes a substrate, a first conductivity type base region formed at a front surface portion of the substrate, a second conductivity type first impurity region formed at the base region, a second conductivity type second impurity region formed at the base region away from the first impurity region, an insulating layer formed on a front surface of the substrate, a first electrode film formed on the insulating layer and electrically connected to the first impurity region, and a second electrode film formed on the insulating layer and electrically connected to the second impurity region, and a first region formed on the insulating layer, the first region being sandwiched between the first electrode film and the second electrode film, and the first region including a portion having an aspect ratio of 1 or larger.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application corresponds to Japanese Patent Application No.2018-135188 filed in the Japan Patent Office on Jul. 18, 2018, and theentire disclosure of the present application is incorporated herein byreference.

TECHNICAL FIELD

The present invention relates to a bidirectional Zener diode and amethod for manufacturing the same.

BACKGROUND ART

A TVS (Transient Voltage Suppressor) element is known as an element thatabsorbs a transient voltage, an ESD (Electrostatic Discharge), noises,etc. The TVS element can be made up of various devices, and, in general,an element in which a pair of diodes are connected in anti-series isemployed as the TVS element. One such example is disclosed in PatentLiterature 1.

A diode having an nppn layered structure that includes an n⁺ typesubstrate, a p⁻ layer formed on a surface layer portion of thesubstrate, a p⁺ layer formed on a surface layer portion of the p layer,and an n⁺ layer formed on a surface layer portion of the p⁺ layer isdisclosed in Patent Literature 1 (description of U.S. Pat. No.6,015,999).

SUMMARY OF INVENTION

Various parameters, such as reverse breakdown voltage V_(BR), reversestandoff voltage V_(rwm), and peak pulse power P_(pk) ((=clampingvoltage V_(CL)×peak pulse current I_(pp)), exist as electricalproperties of a TVS element in which a pair of diodes are connected inanti-series.

Here, the present inventors have considered making a bidirectional Zenerdiode in which a pair of Zener diodes are connected in anti-series on asurface portion of a substrate as a TVS element, unlike the nppn layeredstructure of Patent Literature 1.

In view of these circumstances, the present invention aims to provide abidirectional Zener diode that is capable of achieving more excellentelectrical properties (particularly, peak pulse power P_(pk)) than inconventional techniques and to provide a method for manufacturing thesame.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic perspective view of a bidirectional Zener diodeaccording to a preferred embodiment of the present invention.

FIG. 2 is a plan view of the bidirectional Zener diode of FIG. 1.

FIG. 3A is a longitudinal sectional view along line IIIA-IIIA of FIG. 2.

FIG. 3B is a longitudinal sectional view along line IIIB-IIIB of FIG. 2.

FIG. 4 is a transverse sectional view along line IV-IV of FIG. 3A.

FIG. 5 is an enlarged view of a main portion of FIG. 4.

FIG. 6 is a longitudinal sectional view along line VI-VI of FIG. 5.

FIG. 7 is a flowchart to describe an example of a manufacturing processof the bidirectional Zener diode of FIG. 1.

FIG. 8A to FIG. 8H are views of the manufacturing process of thebidirectional Zener diode of FIG. 1 shown in order of steps.

FIG. 9 is a view showing a current surge waveform in a surge immunitytest.

FIG. 10 is a view showing a current surge waveform in a surge immunitytest.

FIG. 11 is a view showing a relationship between a peak pulse current(I_(pp)) and a clamping voltage (V_(CL)).

FIG. 12 is a view showing a modification of the bidirectional Zenerdiode of FIG. 1.

FIG. 13 is a view showing a modification of the bidirectional Zenerdiode of FIG. 1.

FIG. 14 is a view showing a modification of the bidirectional Zenerdiode of FIG. 1.

DESCRIPTION OF EMBODIMENTS

A bidirectional Zener diode according to one preferred embodiment of thepresent invention includes a substrate, a first conductivity type baseregion formed at a front surface portion of the substrate, a secondconductivity type first impurity region formed at the base region, asecond conductivity type second impurity region formed at the baseregion away from the first impurity region, an insulating layer formedon a front surface of the substrate, a first electrode film formed onthe insulating layer and electrically connected to the first impurityregion, and a second electrode film formed on the insulating layer andelectrically connected to the second impurity region, and, a firstregion formed on the insulating layer, the first region being sandwichedbetween the first electrode film and the second electrode film, and thefirst region including a portion having an aspect ratio of 1 or larger.

According to the bidirectional Zener diode according to one preferredembodiment of the present invention, the first region includes a portionwhose aspect ratio is 1 or larger, and therefore a relatively thickelectrode film is formed as the first electrode film and as the secondelectrode film. This makes it possible to restrict the resistance valueof the first electrode film and the resistance value of the secondelectrode film to a lower value, and makes it possible to allow a largeelectric current to run through these electrode films. As a result, itis possible to heighten the peak pulse current I_(pp) of thebidirectional Zener diode, hence making it possible to achieve excellentpeak pulse power P_(pk).

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the first electrode film may include a firstpad portion disposed away from the first impurity region in a directionalong the front surface of the substrate and a first wiring portion thatextends from the first pad portion to a region on the first impurityregion, and the first wiring portion may have a largest first width (W₁)in a connection portion connected to the first pad portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the first wiring portion may be formed in atapered shape so as to become gradually thinner toward a tip end portionof the first wiring portion from the connection portion connected to thefirst pad portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the largest first width (W₁) in the connectionportion connected to the first pad portion of the first wiring portionmay be twice or more a width (W₁′) of the tip end portion of the firstwiring portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the second electrode film may include a secondpad portion disposed away from the second impurity region in a directionalong the front surface of the substrate and a second wiring portionthat extends from the second pad portion to a region on the secondimpurity region, and the second wiring portion may have a largest secondwidth (W₂) in a connection portion connected to the second pad portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the second wiring portion may be formed in atapered shape so as to become gradually thinner toward a tip end portionof the second wiring portion from the connection portion connected tothe second pad portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the largest second width (W₂) in theconnection portion connected to the second pad portion of the secondwiring portion may be twice or more a width (W₂′) of the tip end portionof the second wiring portion.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, a thickness (T₁) of the first electrode filmand a thickness (T₂) of the second electrode film may be each 3 μm to 5μm, and a distance (D) between the first electrode film and the secondelectrode film in the portion having the aspect ratio (A) of the firstregion may be 0.5 μm to 5 μm.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the first electrode film and the secondelectrode film may be each made of AlCu.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the insulating layer may have a first contacthole that exposes the first impurity region, and the first electrodefilm may be connected to the first impurity region through the firstcontact hole, and the insulating layer may include a first portion thathas a first thickness (T₃) and that forms the first contact hole and asecond portion that surrounds the first portion and that has a secondthickness (T₄) larger than the first thickness (T₃).

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the insulating layer may include a thirdportion that is formed between the first portion and the second portionand that has a third thickness (T₅) smaller than the first thickness(T₃).

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the insulating layer may have a second contacthole that exposes the second impurity region, and the second electrodefilm may be connected to the second impurity region through the secondcontact hole, and the insulating layer may include a fourth portion thathas a fourth thickness (T₆) and that forms the second contact hole and afifth portion that surrounds the fourth portion and that has a fifththickness (T₇) larger than the fourth thickness (T₆).

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the insulating layer may include a sixthportion that is formed between the fourth portion and the fifth portionand that has a sixth thickness (T₈) smaller than the fourth thickness(T₆).

In the bidirectional Zener diode according to one preferred embodimentof the present invention, a plurality of the first impurity regions anda plurality of the second impurity regions may be alternately arrayedalong a predetermined array direction.

The bidirectional Zener diode according to one preferred embodiment ofthe present invention may include a first external electrode that isconnected to the first electrode film and that has a front surfaceincluding a plurality of first convex portions partitioned by a firstgroove and a second external electrode that is connected to the secondelectrode film and that has a front surface including a plurality ofsecond convex portions partitioned by a second groove.

In the bidirectional Zener diode according to one preferred embodimentof the present invention, the plurality of first convex portions and theplurality of second convex portions may be each arrayed in a staggeredmanner.

A method for manufacturing a bidirectional Zener diode according to onepreferred embodiment of the present invention includes a step ofimplanting a second conductivity type impurity into a first conductivitytype base region formed at a front surface portion of a substrate andthen forming a first impurity region and a second impurity region awayfrom each other by applying heat treatment, a step of forming aninsulating layer on a front surface of the substrate, a step of formingan electrode film on the insulating layer so as to be electricallyconnected to the first impurity region and to the second impurityregion, and a step of applying dry etching to the electrode film andhence forming the electrode film into an electrode pattern that includesa first electrode film electrically connected to the first impurityregion and a second electrode film electrically connected to the secondimpurity region, and, in the bidirectional Zener diode, the electrodepattern has a first region that is sandwiched between the firstelectrode film and the second electrode film and that includes a portionhaving an aspect ratio (A) of 1 or larger.

Preferred embodiments of the present invention will be hereinafterdescribed in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view of a bidirectional Zener diode 1according to a preferred embodiment of the present invention. FIG. 2 isa plan view of the bidirectional Zener diode 1 of FIG. 1. FIG. 3A is alongitudinal sectional view along line IIIA-IIIA of FIG. 2. FIG. 3B is alongitudinal sectional view along line IIIB-IIIB of FIG. 2. FIG. 4 is atransverse sectional view along line IV-IV of FIG. 3A. In FIG. 1, aconcavoconvex surface of a first external electrode 7 and aconcavoconvex surface of a second external electrode 8 are omitted.Additionally, in FIG. 3B, first impurity region groups 9 and secondimpurity region groups 10 are depicted by reducing the number of thoseimpurity region groups from the viewpoint of visual clarity.

The bidirectional Zener diode 1 includes a substrate 2 formed in asubstantially rectangular parallelepiped shape. The substrate 2 may be asilicon substrate. The length L1 of a long side in a longitudinaldirection of the substrate 2 is, for example, 0.4 mm to 2 mm. The lengthL2 of a short side in a lateral direction of the substrate 2 is, forexample, 0.2 mm to 2 mm. The thickness T of the substrate 2 is, forexample, 0.1 mm to 0.5 mm. The employment of the substrate 2 having thissize makes it possible to form the bidirectional Zener diode 1 as aso-called chip component, hence making it possible to apply thebidirectional Zener diode 1 to various applications.

The substrate 2 has a first plane 3, a second plane 4 on the sideopposite to the first plane 3, and a third plane 5 by which the firstplane 3 and the second plane 4 are connected together. The first plane 3and the second plane 4 of the substrate 2 are each formed in arectangular shape in a plan view when seen from the normal direction ofthe first and second planes 3 and 4 (hereinafter, referred to simply as“in a plan view”). The first plane 3, the second plane 4, and the thirdplane 5 of the substrate 2 may be referred to as a front surface, a rearsurface, and a side surface of the substrate 2, respectively.Additionally, in the present preferred embodiment, the third plane 5 ispartitioned into four planes in total, i.e., is partitioned into a pairof planes that face each other in the longitudinal direction of thesubstrate 2 and a pair of planes that face each other in the lateraldirection of the substrate 2 because of the fact that the substrate 2 isformed in a rectangular shape in a plan view. On the other hand, even ifthe substrate 2 is, for example, circular in a plan view, ellipsoidal ina plan view, or rectangular in a plan view, the third plane 5 may not benecessarily required to be clearly partitioned into a plurality ofplanes unlike that of FIG. 1 if each corner portion is chamfered.

Referring to FIG. 3A and FIG. 3B, a p type base region 6 is formed inthe substrate 2 and is exposed from the first plane 3 of the substrate2. In the present preferred embodiment, p type impurities are introducedinto the entirety in a thickness direction of the substrate 2 from thefirst plane 3 to the second plane 4 of the substrate 2. Hence, the baseregion 6 is formed in the whole region of the substrate 2, and thesubstrate 2 is configured to be regarded as a p type substrate. Thespecific resistance of the substrate 2 may be set at about 5 mΩ·cm byintroducing p type impurities.

A first external electrode 7 and a second external electrode 8 areformed on the first plane 3 of the substrate 2. The first externalelectrode 7 is formed at one end portion in the longitudinal directionof the substrate 2. The second external electrode 8 is formed at theother end portion in the longitudinal direction of the substrate 2.

Referring to FIG. 3A, FIG. 3B, and FIG. 4, a plurality of (in thepresent preferred embodiment, six) first impurity region groups 9 and aplurality of (in the present preferred embodiment, six) second impurityregion groups 10, which are electrically connected to the first externalelectrode 7 and the second external electrode 8, are formed at a frontsurface portion of the base region 6 between the first externalelectrode 7 and the second external electrode 8.

The first impurity region group 9 extends in the longitudinal directionof the substrate 2, and includes a plurality of (in the presentpreferred embodiment, two) n type first impurity regions 11 that arearranged with an interval between the first impurity regions 11 in thelongitudinal direction of the substrate 2. The second impurity regiongroup 10 extends in parallel with the first impurity region group 9, andincludes a plurality of (in the present preferred embodiment, two) ntype second impurity regions 12 that are arranged with an intervalbetween the second impurity regions 12 in the longitudinal direction ofthe substrate 2. The first impurity region group 9 and the secondimpurity region group 10 are alternately arranged in the lateraldirection of the substrate 2, and have a stripe shape as a whole.

The first impurity region 11 and the second impurity region 12 areadjacent to each other in the lateral direction of the substrate 2.Therefore, likewise, the first impurity region 11 and the secondimpurity region 12 are alternately arranged in the lateral direction ofthe substrate 2. As thus described, the first impurity region 11 and thesecond impurity region 12 are arranged in a 12-row×2-column matrixmanner at the first plane 3 of the substrate 2.

In FIG. 4, the first impurity region groups 9 are formed ateven-numbered rows, respectively, and the second impurity region groups10 are formed at odd-numbered rows, respectively if the rows are definedas a first row, a second row, . . . , and a twelfth row in order fromthe upper side and if the columns are defined as a first column and asecond column in order from the left side. In each of the first impurityregion groups 9, the first impurity region 11 is formed at the firstcolumn and at the second column one by one. Likewise, in each of thesecond impurity region groups 10, the second impurity region 12 isformed at the first column and at the second column one by one.

The first impurity region 11 and the second impurity region 12 may beformed with the same depth and the same n type impurity concentration.Each n type impurity concentration of the first and second impurityregions 11 and 12 may be, for example, 1.0×10¹⁹ cm⁻³ to 1.0×10²¹ cm⁻³.The first impurity region 11 and the second impurity region 12 are eachformed to have the same shape and the same area in a plan view shown inFIG. 4. The first impurity region 11 and the second impurity region 12extend in the longitudinal direction of the substrate 2 in a plan view,and are each formed in a rectangular shape whose four corners are cutoff (i.e., a rectangular shape whose angles are rounded off).

The first impurity region 11 makes a pn junction with the base region 6.A first Zener diode D₁ is formed by a pn junction portion between thefirst impurity region 11 and the base region 6. On the other hand, thesecond impurity region 12 makes a pn junction with the base region 6. Asecond Zener diode D₂ is formed by a pn junction portion between thesecond impurity region 12 and the base region 6. The first Zener diodeD₁ and the second Zener diode D₂ are connected in anti-series throughthe base region 6. The first impurity region 11 and the second impurityregion 12 are formed with an interval between the first impurity region11 and the second impurity region 12 so that a depletion layer spreadingfrom the pn junction portion between the first impurity region 11 andthe base region 6 and a depletion layer spreading from the pn junctionportion between the second impurity region 12 and the base region 6 donot overlap with each other.

A surface insulating film 13 is formed at the first plane 3 of thesubstrate 2. The surface insulating film 13 covers substantially thewhole area of the first plane 3 of the substrate 2. Therefore, thesurface insulating film 13 is formed in a quadrangular shape thatmatches the first plane 3 of the substrate 2 in a plan view. The surfaceinsulating film 13 may include one of or both of an oxide film (SiO₂film) and a nitride film (SiN film). Additionally, the surfaceinsulating film 13 may have a thickness of, for example, 0.1 μm to 2 μm.

A first contact hole 14 by which the first impurity region 11 is exposedand a second contact hole 15 by which the second impurity region 12 isexposed are formed in the surface insulating film 13.

A first electrode film 16 and a second electrode film 17 are formed onthe surface insulating film 13 with an interval between the firstelectrode film 16 and the second electrode film 17.

The first electrode film 16 integrally includes a first pad portion 18and a plurality of first wiring portions 19. The first pad portion 18 isformed in a substantially rectangular shape in a plan view, and isformed at one end portion in the longitudinal direction of the substrate2. The plurality of first wiring portions 19 are linearly drawn out fromthe first pad portion 18 toward the second pad portion 20 in thelongitudinal direction of the substrate 2 and cover the plurality offirst impurity region groups 9, respectively, with a one-on-onecorrespondence relationship. Each of the first wiring portions 19 islarger in width than the first impurity region 11. The first wiringportion 19 enters the first contact hole 14 from above the surfaceinsulating film 13, and makes an ohmic contact with the first impurityregion 11.

The second electrode film 17 integrally includes a second pad portion 20and a plurality of second wiring portions 21. The second pad portion 20is formed in a substantially rectangular shape in a plan view, and isformed at the other end portion in the longitudinal direction of thesubstrate 2. The plurality of second wiring portions 21 are linearlydrawn out from the second pad portion 20 toward the first pad portion 18in the longitudinal direction of the substrate 2 and cover the pluralityof second impurity region groups 10, respectively, with a one-on-onecorrespondence relationship. Each of the second wiring portions 21 islarger in width than the second impurity region 12. The second wiringportion 21 enters the second contact hole 15 from above the surfaceinsulating film 13, and makes an ohmic contact with the second impurityregion 12.

The first wiring portion 19 and the second wiring portion 21 are eachformed in a comb-teeth shape so that the first and second wiringportions 19 and 21 engage each other. The first wiring portion 19 andthe second wiring portion 21 are electrically insulated by a slit 22with which their peripheral edge portions are rimmed. In each of thefirst and second electrode films 16 and 17, a material including Al maybe used as its electrode material. For example, AlCu, AlSiCu, etc., canbe mentioned as such a material, and it is preferable to use AlCu fromthe viewpoint of heightening a peak pulse current I_(pp).

An insulating layer 23 is formed on the surface insulating film 13. Theinsulating layer 23 covers the first electrode film 16 and the secondelectrode film 17. The insulating layer 23 includes a first insulatingfilm 24 and a second insulating film 25 that are stacked in this orderfrom the surface-insulating-film-13 side. The first insulating film 24may include one of or both of, for example, an oxide film (SiO₂ film)and a nitride film (SiN film). The second insulating film 25 may includean insulating resin such as polyimide. Additionally, the insulatinglayer 23 may have a thickness of, for example, 1 μm to 10 μm. In thepresent preferred embodiment, the thickness of the first insulating film24 may be, for example, 0.5 μm to 2 μm, and the thickness of the secondinsulating film 25 may be, for example, 0.5 μm to 8 μm.

A first opening 26 and a second opening 27 are formed in the insulatinglayer 23. The first opening 26 exposes the first pad portion 18 of thefirst electrode film 16. The second opening 27 exposes the second padportion 20 of the second electrode film 17.

The first external electrode 7 is formed in the first opening 26. Thefirst external electrode 7 is electrically connected to the firstelectrode film 16 in the first opening 26. Hence, the first externalelectrode 7 is electrically connected to each of the first impurityregions 11 through the first electrode film 16. Additionally, the firstexternal electrode 7 functions as a terminal when the bidirectionalZener diode 1 is mounted according to flip-chip packaging, and thereforethe first external electrode 7 may be referred to as a first externalterminal.

The first external electrode 7 protrudes from the insulating layer 23.Additionally, the first external electrode 7 may have a layeredstructure in which a plurality of metal films are stacked together. Theplurality of metal films may include an Ni film, a Pd film, and an Aufilm stacked in this order from the first-electrode-film-16 side.

The second external electrode 8 is formed in the second opening 27. Thesecond external electrode 8 is electrically connected to the secondelectrode film 17 in the second opening 27. Hence, the second externalelectrode 8 is electrically connected to each of the second impurityregions 12 through the second electrode film 17. Additionally, thesecond external electrode 8 functions as a terminal when thebidirectional Zener diode 1 is mounted according to flip-chip packaging,and therefore the second external electrode 8 may be referred to as asecond external terminal.

The second external electrode 8 is formed protrudes from the insulatinglayer 23. The second external electrode 8 may have a layered structurein which a plurality of metal films are stacked together. The pluralityof metal films may include an Ni film, a Pd film, and an Au film stackedin this order from the second-electrode-film-17 side.

Referring to FIG. 2, FIG. 3A, and FIG. 3B, the first external electrode7 is formed in a substantially rectangular shape that is long in thelateral direction of the substrate 2 in a plan view. Corner portions ofthe first external electrode 7 respectively formed at the cornerportions of the substrate 2 are chamfered, and, as a result, the firstexternal electrode 7 has corner planes 28 facing the corner portions ofthe substrate 2 at the pair of corner portions, respectively.Additionally, the first external electrode 7 is formed in aline-symmetric shape with respect to a symmetric axis A along thelongitudinal direction of the substrate 2.

A first flat portion 29 and a plurality of first convex portions 30 areformed on a front surface of the first external electrode 7. The firstflat portion 29 is a portion of the first external electrode 7 whosefront surface is flattened, and is formed near one of the pair of cornerplanes 28 (corner portions) of the first external electrode 7. In thepresent preferred embodiment, the first flat portion 29 is formed in aquadrangular shape in a plan view.

The plurality of first convex portions 30 are formed around the firstflat portion 29 of the first external electrode 7, and define undulationin regions other than the first flat portion 29 of the front surface ofthe first external electrode 7. In the present preferred embodiment,each of the first convex portions 30 is formed in a quadrangular shapein a plan view. The plurality of first convex portions 30 have a surfacearea smaller than the first flat portion 29. In the present preferredembodiment, the first convex portions 30 are in a partitioned state in astaggered array by means of a first groove 31 formed at the frontsurface of the first external electrode 7.

Referring to FIG. 2, FIG. 3A, and FIG. 3B, the second external electrode8 is formed in a substantially rectangular shape that is long in thelateral direction of the substrate 2 in a plan view. Corner portions ofthe second external electrode 8 respectively formed at the cornerportions of the substrate 2 are chamfered, and, as a result, the secondexternal electrode 8 has a first corner plane 32 and a second cornerplane 33 facing the corner portions of the substrate 2 at the pair ofcorner portions, respectively. In the present preferred embodiment, thewidth (amount of chamfering) of the second corner plane 33 is largerthan the width (amount of chamfering) of the first corner plane 32 (forexample, five to ten times). Hence, the second external electrode 8 isformed in a non-line-symmetric shape with respect to the symmetric axisA along the longitudinal direction of the substrate 2. Additionally,when the width of the second corner plane 33 is comparatively large, theshape of the second external electrode 8 may be expressed as asubstantially pentagonal shape that is long in the lateral direction ofthe substrate 2 if the width of the second corner plane 33 and thelength of a side along the longitudinal direction of the substrate 2continuous with the second corner plane 33 are substantially equal toeach other as in, for example, FIG. 2.

A second flat portion 34 and a plurality of second convex portions 35are formed on a front surface of the second external electrode 8. Thesecond flat portion 34 is a portion of the second external electrode 8whose front surface is flattened, and is formed near the second cornerplane 33 that is one of the pair of corner planes 32 and 33 (cornerportions) of the second external electrode 8. Hence, the first flatportion 29 of the first external electrode 7 and the second flat portion34 of the second external electrode 8 are formed at the corner portionsof the substrate 2 having a diagonal relationship, respectively.Additionally, in the present preferred embodiment, the second flatportion 34 is formed in an isosceles triangle shape (more specifically,an isosceles right triangle shape) in which a side along the secondcorner plane 33 is a base side in a plan view.

The plurality of second convex portions 35 are formed around the secondflat portion 34 of the second external electrode 8, and defineundulation in regions other than the second flat portion 34 of the frontsurface of the second external electrode 8. In the present preferredembodiment, each of the second convex portions 35 is formed in aquadrangular shape in a plan view. The plurality of second convexportions 35 have a surface area smaller than the second flat portion 34.In the present preferred embodiment, the second convex portions 35 arein a partitioned state in a staggered array by means of a second groove36 formed at the front surface of the second external electrode 8.

According to the thus formed first and second external electrodes 7 and8, when light is projected onto the front surface of each of the firstand second external electrodes 7 and 8, it is possible to diffuselyreflect the light in an excellent manner by means of the concave-convexsurface formed by both the first convex portion 30 and the first groove31 and by means of the concave-convex surface formed by both the secondconvex portion 35 and the second groove 36. This makes it possible toexcellently ascertain the first external electrode 7 and the secondexternal electrode 8, thus making it possible to easily make afront-or-back determination about the bidirectional Zener diode 1.

Additionally, it is possible to press a tip end portion of a probeagainst the first and second flat portions 29 and 34 of the first andsecond external electrodes 7 and 8, respectively, when an electric testis performed, hence making it possible to excellently measure electricalproperties of the bidirectional Zener diode 1. Moreover, the first flatportion 29 and the second flat portion 34 are positionally in a mutuallydiagonal relationship, and are comparatively distant from each other ina surface region of the substrate 2, and therefore it is possible toefficiently perform an electric test by use of the probe.

Additionally, the first external electrode 7 has a line-symmetric shape,and the second external electrode 8 has a non-line-symmetric shape, andtherefore it is possible to easily determine whether it is the firstexternal electrode 7 or the second external electrode 8.

Additionally, it is possible to increase the surface area of the frontsurface of each of the first and second external electrodes 7 and 8 bymeans of concavo-convex portions provided at the front surface of eachof the first and second external electrodes 7 and 8. This makes itpossible to increase the contact area between the front surface of eachof the first and second external electrodes 7 and 8 and a joiningmaterial, such as solder, when the bidirectional Zener diode 1 ismounted on a mounting board by use of the joining material. Therefore,it is possible to excellently mount the bidirectional Zener diode 1 onthe mounting board.

Additionally, the concavo-convex portions provided at the front surfaceof each of the first and second external electrodes 7 and 8 also make itpossible to prevent insulating foreign substances existing at the tipend portion of the probe from adhering to the front surface of each ofthe first and second external electrodes 7 and 8 when an electric testis performed.

Referring to FIG. 4, the first pad portion 18 of the first electrodefilm 16 and the second pad portion 20 of the second electrode film 17have planar shapes that coincide with planar shapes of the first andsecond external electrodes 7 and 8, respectively.

In other words, the first pad portion 18 is formed in a substantiallyrectangular shape that is long in the lateral direction of the substrate2 in a plan view. Corner portions of the first pad portion 18respectively formed at the corner portions of the substrate 2 arechamfered, and, as a result, the first pad portion 18 has corner planes37 facing the corner portions of the substrate 2 at the pair of cornerportions, respectively. Additionally, the first pad portion 18 is formedin a line-symmetric shape with respect to the symmetric axis A along thelongitudinal direction of the substrate 2.

A first flat portion 38 and a plurality of first convex portions 39 areformed on a front surface of the first pad portion 18. The first flatportion 38 is a portion of the first pad portion 18 whose front surfaceis flattened, and is formed near one of the pair of corner planes 37(corner portions) of the first pad portion 18. In the present preferredembodiment, the first flat portion 38 is formed in a quadrangular shapein a plan view.

The plurality of first convex portions 39 are formed around the firstflat portion 38 of the first pad portion 18, and define undulation inregions other than the first flat portion 38 of the front surface of thefirst pad portion 18. In the present preferred embodiment, each of thefirst convex portions 39 is formed in a quadrangular shape in a planview. The plurality of first convex portions 39 have a surface areasmaller than the first flat portion 38. In the present preferredembodiment, the plurality of first convex portions 39 are in apartitioned state in a staggered array by means of a first groove 40formed at the front surface of the first pad portion 18.

The second pad portion 20 is formed in a substantially rectangular shapethat is long in the lateral direction of the substrate 2 in a plan view.Corner portions of the second pad portion 20 respectively formed at thecorner portions of the substrate 2 are chamfered, and, as a result, thesecond pad portion 20 has a first corner plane 41 and a second cornerplane 42 facing the corner portions of the substrate 2 at the pair ofcorner portions, respectively. In the present preferred embodiment, thewidth (amount of chamfering) of the second corner plane 42 is largerthan the width (amount of chamfering) of the first corner plane 41 (forexample, five to ten times). Hence, the second pad portion 20 is formedin a non-line-symmetric shape with respect to the symmetric axis A alongthe longitudinal direction of the substrate 2. Additionally, when thewidth of the second corner plane 42 is comparatively large, the shape ofthe second pad portion 20 may be expressed as a substantially pentagonalshape that is long in the lateral direction of the substrate 2 if thewidth of the second corner plane 42 and the length of a side along thelongitudinal direction of the substrate 2 continuous with the secondcorner plane 42 are substantially equal to each other as in, forexample, FIG. 4.

A second flat portion 43 and a plurality of second convex portions 44are formed on a front surface of the second pad portion 20. The secondflat portion 43 is a portion of the second pad portion 20 whose frontsurface is flattened, and is formed near the second corner plane 42 thatis one of the pair of corner planes 41 and 42 (corner portions) of thesecond pad portion 20. Hence, the first flat portion 38 of the first padportion 18 and the second flat portion 43 of the second pad portion 20are formed at the corner portions of the substrate 2 having a diagonalrelationship, respectively. Additionally, in the present preferredembodiment, the second flat portion 43 is formed in an isoscelestriangle shape (more specifically, an isosceles right triangle shape) inwhich a side along the second corner plane 42 is a base side in a planview.

The plurality of second convex portions 44 are formed around the secondflat portion 43 of the second pad portion 20, and define undulation inregions other than the second flat portion 43 of the front surface ofthe second pad portion 20. In the present preferred embodiment, each ofthe second convex portions 44 is formed in a quadrangular shape in aplan view. The plurality of second convex portions 44 have a surfacearea smaller than the second flat portion 43. In the present preferredembodiment, the plurality of second convex portions 44 are in apartitioned state in a staggered array by means of a second groove 45formed at the front surface of the second pad portion 20.

Referring to FIG. 1, FIG. 3A, and FIG. 3B, an insulating film 46 isformed on the third plane 5 of the substrate 2. The insulating film 46may include one of or both of, for example, an oxide film (SiO₂ film)and a nitride film (SiN film). The insulating film 46 integrally coversthe whole area of the third plane 5 of the substrate 2. On the otherhand, the second plane 4 of the substrate 2 may be covered with theinsulating film 46 (not shown) although the second plane is exposed fromthe insulating film 46 in the present preferred embodiment.Additionally, the insulating film 46 may have a thickness of, forexample, 0.1 μm to 2 μm.

FIG. 5 is an enlarged view of a main portion of FIG. 4. FIG. 6 is alongitudinal sectional view along line VI-VI of FIG. 5. In FIG. 5 andFIG. 6, the first external electrode 7, the second external electrode 8,and the insulating layer 23 are omitted.

Next, the shape of the first electrode film 16, the shape of the secondelectrode film 17, the shape of the surface insulating film 13, etc.,will be described in more detail with reference to FIG. 5 and FIG. 6.

First, referring to FIG. 6, the surface insulating film 13 includes afirst portion 47, a second portion 48, and a third portion 49, whichdiffer from each other in thickness, around the first contact hole 14.

The first portion 47 is partially buried in the substrate 2 with respectto the first plane 3 of the substrate 2. In the present preferredembodiment, substantially half the first portion 47 in the thicknessdirection of the first portion 47 is buried in the substrate 2, and theremaining half is formed on the first plane 3 of the substrate 2.Additionally, the first portion 47 defines the first contact hole 14.The first contact hole 14 is formed in a tapered shape so as to becomegradually thinner toward the substrate 2 from the front surface of thesurface insulating film 13 in the first portion 47. Additionally, thefirst portion 47 has a first thickness T₃ that may be, for example, 0.2μm to 1 μm.

The entirety of the second portion 48 is formed on the first plane 3 ofthe substrate 2. The second portion 48 is a portion that covers most ofthe surface insulating film 13, except for the first portion 47 and thethird portion 49 that are formed near the first contact hole 14. Thesecond portion 48 surrounds the first portion 47 around the firstcontact hole 14. Additionally, the second portion 48 has a secondthickness T₄ larger than the first thickness T₃, and the secondthickness T₄ may be, for example, 0.5 μm to 2 μm.

The third portion 49 is partially buried in the substrate 2 with respectto the first plane 3 of the substrate 2 in the same way as the firstportion 47. In the present preferred embodiment, substantially half thethird portion 49 in the thickness direction of the third portion 49 isburied in the substrate 2, and the remaining half is formed on the firstplane 3 of the substrate 2. The third portion 49 is formed between thefirst portion 47 and the second portion 48. In other words, the thirdportion 49 surrounds the first portion 47, and the second portion 48surrounds the third portion 49. The first portion 47 and the secondportion 48 are connected together by means of the third portion 49. Thethird portion 49 has a third thickness T₅ smaller than the firstthickness T₃, and the third thickness T₅ may be, for example, 0.1 μm to0.5 μm.

As thus described, there is a film thickness difference between thefirst portion 47 and the second portion 48, and, because of this filmthickness difference, a concave portion 50 is formed around the firstcontact hole 14 at the surface insulating film 13. A bottom surface 52of the concave portion 50 is formed of the first portion 47, and a sidesurface 51 of the concave portion 50 is formed of the second portion 48.The third portion 49 may form a part of the bottom surface 52 of theconcave portion 50.

The side surface 51 of the concave portion 50 is formed in a taperedshape so as to become gradually thinner toward the substrate 2 from thefront surface of the surface insulating film 13 in the present preferredembodiment.

Additionally, a level difference that results from a film thicknessdifference between the first portion 47 and the third portion 49 may beformed at a boundary portion between the first portion 47 and the thirdportion 49 at the bottom surface 52 of the concave portion 50.Additionally, in the bottom surface 52 of the concave portion 50, theboundary portion between the first portion 47 and the third portion 49may be an oblique surface 53 that spreads from the first portion 47toward the third portion 49. This oblique surface 53 is formed on therear surface side of the surface insulating film (i.e., on the sidecontiguous to the substrate 2), and therefore the boundary portionbetween the first portion 47 and the third portion 49 may be a portionin which its thickness becomes continuously smaller in proportion toreceding from the first contact hole 14.

The surface insulating film 13 includes a fourth portion 54, a fifthportion 55, and a sixth portion 56, which differ from each other inthickness, around the second contact hole 15.

The fourth portion 54 is partially buried in the substrate 2 withrespect to the first plane 3 of the substrate 2. In the presentpreferred embodiment, substantially half the fourth portion 54 in thethickness direction of the fourth portion 54 is buried in the substrate2, and the remaining half is formed on the first plane 3 of thesubstrate 2. Additionally, the fourth portion 54 defines the secondcontact hole 15. The second contact hole 15 is formed in a tapered shapeso as to become gradually thinner toward the substrate 2 from the frontsurface of the surface insulating film 13 in the fourth portion 54.Additionally, the fourth portion 54 has a fourth thickness T₆ that maybe, for example, 0.2 μm to 1 μm.

The entirety of the fifth portion 55 is formed on the first plane 3 ofthe substrate 2. The fifth portion 55 is a portion that covers most ofthe surface insulating film 13, except for the fourth portion 54 and thesixth portion 56 that are formed near the second contact hole 15, andthe fifth portion 55 may include a portion shared with theaforementioned second portion 48. The fifth portion 55 surrounds thefourth portion 54 around the second contact hole 15. Additionally, thefifth portion 55 has a fifth thickness T₇ larger than the fourththickness T₆, and the fifth thickness T₇ may be, for example, 0.5 μm to2 μm.

The sixth portion 56 is partially buried in the substrate 2 with respectto the first plane 3 of the substrate 2 in the same way as the fourthportion 54. In the present preferred embodiment, substantially half thesixth portion 56 in the thickness direction of the sixth portion 56 isburied in the substrate 2, and the remaining half is formed on the firstplane 3 of the substrate 2. The sixth portion 56 is formed between thefourth portion 54 and the fifth portion 55. In other words, the sixthportion 56 surrounds the fourth portion 54, and the fifth portion 55surrounds the sixth portion 56. The fourth portion 54 and the fifthportion 55 are connected together by means of the sixth portion 56.Additionally, the sixth portion 56 has a sixth thickness T₈ smaller thanthe fourth thickness T₆, and the sixth thickness T₈ may be, for example,0.1 μm to 0.5 μm.

As thus described, there is a film thickness difference between thefourth portion 54 and the fifth portion 55, and, because of this filmthickness difference, a concave portion 57 is formed around the secondcontact hole 15 at the surface insulating film 13. A bottom surface 59of the concave portion 57 is formed of the fourth portion 54, and a sidesurface 58 of the concave portion 57 is formed of the fifth portion 55.The sixth portion 56 may forma part of the bottom surface 59 of theconcave portion 57.

The side surface 58 of the concave portion 57 is formed in a taperedshape so as to become gradually thinner toward the substrate 2 from thefront surface of the surface insulating film 13 in the present preferredembodiment.

Additionally, a level difference that results from a film thicknessdifference between the fourth portion 54 and the sixth portion 56 may beformed at a boundary portion between the fourth portion 54 and the sixthportion 56 at the bottom surface 59 of the concave portion 57.Additionally, in the bottom surface 59 of the concave portion 57, theboundary portion between the fourth portion 54 and the sixth portion 56may be an oblique surface 60 that spreads from the fourth portion 54toward the sixth portion 56. This oblique surface 60 is formed on therear surface side of the surface insulating film 13 as well (i.e., onthe side contiguous to the substrate 2), and therefore the boundaryportion between the fourth portion 54 and the sixth portion 56 may be aportion in which its thickness becomes continuously smaller inproportion to receding from the second contact hole 15.

Referring to FIG. 6, the first impurity region 11 has an extent thatstraddles over the first portion 47, the third portion 49, and thesecond portion 48 of the surface insulating film 13, and the firstimpurity region 11 covers the first portion 47, the third portion 49,and the second portion 48 from below. On the other hand, referring toFIG. 6, the second impurity region 12 has an extent that straddles overthe fourth portion 54, the sixth portion 56, and the fifth portion 55 ofthe surface insulating film 13, and the second impurity region 12 coversthe fourth portion 54, the sixth portion 56, and the fifth portion 55from below.

Next, referring to FIG. 5, the first wiring portion 19 of the firstelectrode film 16 is formed in a tapered shape so as to become graduallythinner toward the second pad portion 20 from a connection portion 61connected to the first pad portion 18. Hence, the first wiring portion19 has the largest width W₁ in the connection portion 61 connected tothe first pad portion 18, and has the minimum width in a tip end portion62. In other words, the width of the first wiring portion 19 becomescontinuously smaller in proportion to a progression from the connectionportion 61 toward the tip end portion 62. For example, the maximum widthW₁ may be twice or more the minimum width W₁′. More specifically, thewidth W₁ may be, for example, 6 μm to 12 μm, and the width W₁′ may be,for example, 5 μm to 10 μm. It is recommended to set the width of aportion between the connection portion 61 and the tip end portion 62 soas to fall within a range between the maximum width W₁ and the minimumwidth W₁′.

Referring to FIG. 5, the second wiring portion 21 of the secondelectrode film 17 is formed in a tapered shape so as to become graduallythinner toward the second pad portion 20 from a connection portion 63connected to the second pad portion 20. Hence, the second wiring portion21 has the largest width W₂ in the connection portion 63 connected tothe second pad portion 20, and has the minimum width W₂′ in a tip endportion 64. In other words, the width of the second wiring portion 21becomes continuously smaller in proportion to a progression from theconnection portion 63 toward the tip end portion 64. For example, themaximum width W₂ may be twice or more the minimum width W₂′. Morespecifically, the width W₂ may be, for example, 6 μm to 12 μm, and thewidth W₂′ may be, for example, 5 μm to 10 μm. It is recommended to setthe width of a portion between the connection portion 63 and the tip endportion 64 so as to fall within a range between the maximum width W₂ andthe minimum width W₂′.

Next, referring to FIG. 6, the first wiring portion 19 of the firstelectrode film 16 has an extent (width) in which the first wiringportion 19 straddles over the first portion 47, the third portion 49,and the second portion 48 of the surface insulating film 13, and thefirst wiring portion 19 covers the first portion 47, the third portion49, and the second portion 48 from above. In the present preferredembodiment, the first wiring portion 19 has a width larger than thefirst impurity region 11. On the other hand, the second wiring portion21 of the second electrode film 17 has an extent (width) in which thesecond wiring portion 21 straddles over the fourth portion 54, the sixthportion 56, and the fifth portion 55 of the surface insulating film 13,and the second wiring portion 21 covers the fourth portion 54, the sixthportion 56 and the fifth portion 55 from above. In the present preferredembodiment, the second wiring portion 21 has a width larger than thesecond impurity region 12.

The first electrode film 16 and the second electrode film 17 have athickness T₁ and a thickness T₂, respectively. These thicknesses T₁ andT₂ may be equal to each other, and are, for example, 3 μm to 5 μm. Thethicknesses T₁ and T₂ may be lengths from the first plane 3 of thesubstrate 2 to an upper surface of the first electrode film 16 and to anupper surface of the second electrode film 17 in the position of thefirst contact hole 14 and in the position of the second contact hole 15,respectively. Additionally, the thicknesses T₁ and T₂ may be lengthsfrom the front surface of the surface insulating film 13 to the uppersurface of the first electrode film 16 and to the upper surface of thesecond electrode film 17, respectively, in an upper surface region ofthe surface insulating film 13.

A part of the first wiring portion 19 on the surface insulating film 13and a part of the second wiring portion 21 on the surface insulatingfilm 13 are leveled up resulting from the thickness of the surfaceinsulating film 13. Hence, the first wiring portion 19 has a curvedupper surface 65 that is concaved from the part of the first wiringportion 19 on the surface insulating film 13 toward the first contacthole 14. Additionally, the second wiring portion 21 has a curved uppersurface 66 that is concaved from the part of the second wiring portion21 on the surface insulating film 13 toward the second contact hole 15.Each side surface of the first and second wiring portions 19 and 21 maybe an oblique surface that spreads from the upper surfaces 65 and 66toward the surface insulating film 13.

As described above, the first wiring portion 19 and the second wiringportion 21 are electrically insulated from each other by means of theslit 22. The width of the slit 22 (i.e., distance D between the firstwiring portion 19 and the second wiring portion 21) is, for example, 0.5μm to 5 μm. If each side surface of the first and second wiring portions19 and 21 is an oblique surface, the slit 22 is formed in a taperedshape so as to become gradually thinner toward the surface insulatingfilm 13. At this time, the distance D may be measured at arbitrarypositions in the thickness direction of the first and second wiringportions 19 and 21.

The thickness T₁ of the first wiring portion 19 and the thickness T₂ ofthe second wiring portion 21 are each 3 μm to 5 μm, and the width D ofthe slit 22 is 0.5 μm to 5 μm, and therefore the slit 22 has an aspectratio A (T₂ or T₂/D) of 1 or larger, and may have, preferably, an aspectratio A of 2 to 4.

FIG. 7 is a flowchart to describe an example of a manufacturing processof the bidirectional Zener diode 1 of FIG. 1. FIG. 8A to FIG. 8H areviews of the manufacturing process of the bidirectional Zener diode 1 ofFIG. 1 shown in order of process steps.

In order to manufacture the bidirectional Zener diode 1, a singledisk-shaped wafer that is a base for the substrate 2 is preparedreferring to, for example, FIG. 8A (Step S1). A plurality of chipregions that become the bidirectional Zener diodes 1 are set at thefirst plane 3 of the wafer. Next, the surface insulating film 13 isformed at the first plane 3 of the wafer by means of, for example,thermal oxidation treatment (Step S2).

Next, referring to FIG. 8B, parts of the surface insulating film 13 thatcover regions in which the first and second impurity regions 11 and 12of the first plane 3 of the wafer are to be formed are selectivelyremoved, and, as a result, a first opening 67 and a second opening 68are formed (Step S3). The surface insulating film 13 may be removed by,for example, wet etching. This makes it possible to form the sidesurface 51 of the first opening 67 and the side surface 58 of the secondopening 68 as oblique surfaces, respectively.

Next, referring to FIG. 8C, an impurity-containing insulating film 69 isdeposited on the surface insulating film 13 by means of, for example, aCVD method (Step S4). The impurity-containing insulating film 69contains an impurity to form the first and second impurity regions 11and 12, and phosphosilicate glass (PSG) that contains phosphorus that isan n type impurity is used in the present preferred embodiment, and yetother insulating films may be used.

Next, referring to FIG. 8D, heat treatment (for example, 900° C. to1200° C.) is performed, and, as a result, phosphorus in theimpurity-containing insulating film 69 is implanted into the p typesubstrate 2, and a first impurity region 70 and a second impurity region71 are formed (Step S5). The first impurity region 70 and the secondimpurity region 71 each has, for example, a peripheral edge thatsubstantially coincides with a peripheral edge of the first opening 67and with a peripheral edge of the second opening 68.

Next, referring to FIG. 8E, the impurity-containing insulating film 69is removed by, for example, wet etching (Step S6). At this time, asurface layer portion of the surface insulating film 13 that existsunder the impurity-containing insulating film 69 is also removed asshown by the broken line in FIG. 8E, and the thickness of the surfaceinsulating film 13 is reduced. As a result of the isotropic removal ofthe surface insulating film 13, the diameter of the first opening 67 andthe diameter of the second opening 68 are also widened, and a portion 72of the base region 6 is exposed between a peripheral edge of the firstopening 67 and a peripheral edge of the first impurity region 70.Likewise, a portion 73 of the base region 6 is exposed between aperipheral edge of the second opening 68 and a peripheral edge of thesecond impurity region 71.

Next, referring to FIG. 8F, an insulating film (oxide film) is formedby, for example, thermal oxidation treatment at the first plane 3 of thesubstrate 2 exposed to the first opening 67 and to the second opening 68(Step S7). This insulating film is formed on upper and lower sides withrespect to the first plane 3 of the substrate 2, and hence is broughtinto a state in which substantially half the insulating film in thethickness direction is buried in the substrate 2. Additionally, in thefirst plane 3 of the substrate 2, there is an impurity concentrationdifference between the first and second impurity regions 70 and 71 andthe portions 72 and 73 of the base region 6 (the concentration of thefirst impurity region 70 and the concentration of the second impurityregion 71 are relatively high). Therefore, an oxidation reaction in thefirst and second impurity regions 70 and 71 progresses more rapidly thanan oxidation reaction in the portions 72 and 73 of the base region 6. Asa result, a thicker insulating film is formed in the first and secondimpurity regions 70 and 71 than in the portions 72 and 73 of the baseregion 6. Hence, the first and fourth portions 47 and 54 of therelatively thick surface insulating film 13 and the third and sixthportions 49 and 56 of the relatively thin surface insulating film 13 areformed. The remaining portions of the surface insulating film 13 are thesecond portion 48 and the fifth portion 55. The first opening 67 and thesecond opening 68 are closed by thermal oxidation, and, as a result, theconcave portion 50 and the concave portion 57 are formed at the positionof the first opening 67 and the position of the second opening 68,respectively.

Next, referring to FIG. 8G, heat treatment (drive-in process) to diffusethe n type impurity implanted in the wafer is performed, and the firstimpurity region 70 and the second impurity region 71 are enlarged, andthe first impurity region 11 and the second impurity region 12 areformed (Step S8). Next, the first contact hole 14 that exposes the firstimpurity region 11 and the second contact hole 15 that exposes thesecond impurity region 12 are formed in the surface insulating film 13by means of, for example, etching in which a mask is used (Step S9).

Next, referring to FIG. 8H, an electrode material is deposited so as tocover the surface insulating film 13 by means of, for example, asputtering method, and an electrode film is formed on the surfaceinsulating film 13 (Step S10). Next, the electrode film is subjected topatterning into a desired shape by means of etching in which a mask isused. Hence, the first electrode film 16 and the second electrode film17 are formed. Dry etching is employed as the etching.

Next, a nitride film is deposited so as to cover the first electrodefilm 16 and the second electrode film 17 by means of, for example, theCVD method, and the first insulating film 24 is formed (Step S11). Next,photosensitive polyimide is applied onto the first insulating film 24,and the second insulating film 25 is formed (Step S12). Next, the secondinsulating film 25 is exposed and developed with patterns correspondingto the first and second openings 26 and 27 (Step S13). Next, the firstinsulating film 24 is etched while using the second insulating film 25as a mask, and the first opening 26 and the second opening 27 are formed(Step S14).

Next, an Ni film, a Pd film, and an Au film are subjected to platingdeposition in this order so as to fill the first and second openings 26and 27 therewith, and the first external electrode 7 and the secondexternal electrode 8 are formed (Step S15). Next, a wafer is subjectedto half-etching for partitioning into chip regions, and grooves forpartitioning into chip regions are formed (Step S16). Next, siliconnitride is deposited on an inner surface of the groove by means of, forexample, the CVD method, and the insulating film 46 is formed (StepS17). Next, a rear surface of the wafer is ground until leading to thegroove (Step S18). Hence, a plurality of bidirectional Zener diodes 1are produced as individual pieces, respectively.

As described above, according to the bidirectional Zener diode 1, theslit 22 includes a portion whose aspect ratio is 1 or larger, andtherefore a relatively thick electrode film is formed as the firstelectrode film 16 (first wiring portion 19) and as the second electrodefilm 17 (second wiring portion 21). This makes it possible to restrictthe resistance value of the first electrode film 16 and the resistancevalue of the second electrode film 17 to a lower value, and makes itpossible to allow a large electric current to run through the electrodefilms 16 and 17. As a result, it is possible to heighten the peak pulsecurrent I_(pp) of the bidirectional Zener diode 1, hence making itpossible to achieve excellent peak pulse power P_(pk).

Additionally, the first wiring portion 19 of the first electrode film 16and the second wiring portion 21 of the second electrode film 17 areeach formed in a tapered shape so as to become gradually thinner inproportion to receding from the first pad portion 18 and from the secondpad portion 20, respectively. The first wiring portion 19 and the secondwiring portion 21 have the maximum widths W₁ and W₂ in the connectionportion 61 connected to the first pad portion 18 and the connectionportion 63 connected to the second pad portion 20, respectively. It ispossible to allow an electric current from the first pad portion 18 andan electric current from the second pad portion 20 to efficiently flowto the first wiring portion 19 and to the second wiring portion 21 byenlarging the width of the connection portion 61 and the width of theconnection portion 63 through which a large electric current flows onthe upstream side of an electric current in the first wiring portion 19and in the second wiring portion 21.

On the other hand, the width becomes smaller toward the tip end portions62 and 64 (downstream side of an electric current) of the first andsecond wiring portions 19 and 21, and it is conceivable that theresistance value will become higher, and yet part of the electriccurrent is consumed in the first and second impurity regions 11 and 12formed halfway during a period during which the electric current flowsto the tip end portions 62 and 64. Therefore, the current value is smallnear the tip end portions 62 and 64, and therefore it is possible toallow the electric current to flow fully efficiently even if the widthof the first wiring portion 19 and the width of the second wiringportion 21 are narrow.

In other words, in the bidirectional Zener diode 1, the first wiringportion 19 and the second wiring portion 21 that engage each other in acomb-teeth manner are each formed in a tapered shape, and therefore itis possible to efficiently form the first electrode film 16 and thesecond electrode film 17 while effectively using the space of thesubstrate 2 that is limited in magnitude, and it is also possible toallow an electric current to flow efficiently.

Next, with respect to the structure of the above-described bidirectionalZener diode 1, surge immunity tests were performed in conformity toIEC61000-4-5, and the results are shown in FIGS. 9 to 11. It has beenunderstood from the results of FIGS. 9 to 11 that the bidirectionalZener diode 1 is capable of achieving a large peak pulse current I_(pp)of 65A and is capable of achieving excellent peak pulse power P_(pk).

Although the preferred embodiment of the present invention has beendescribed as above, the present invention can be embodied in othermodes.

For example, in the aforementioned preferred embodiment, theconductivity type of the base region 6 (substrate 2) and eachconductivity type of the first and second impurity regions 11 and 12 maybe reversed. In other words, the p type portion may be changed into an ntype portion, and the n type portion may be changed into a p typeportion.

Although only the 12-row×2-column matrix is shown as an example of thesequence pattern of each of the first and second impurity regions 11 and12 as described in the aforementioned preferred embodiment, a sequencepattern whose column number is greater than in FIG. 4 (for example, a12-row×4-column matrix) may be employed with reference to, for example,FIG. 12. Additionally, the first impurity region 11 and the secondimpurity region 12 may be arrayed in a stripe manner as a whole byallowing the first impurity region 11 and the second impurity region 12to be formed one by one with respect to one first wiring portion 19 andone second wiring portion 21, respectively, with reference to FIG. 13.

Additionally, the upper surfaces 65 and 66 of the first and secondwiring portions 19 and 21 are not necessarily required to be curved, andmay be flat with reference to FIG. 14.

The bidirectional Zener diode 1 shown in the aforementioned preferredembodiment can be incorporated into, for example, electronic devices,mobile terminals such as portable electronics, robots, drones, etc., asa circuit component for power supply circuits, for high frequencycircuits, for digital circuits, and so on.

Besides, various design changes can be made within the scope of mattersmentioned in the claims.

What is claimed is:
 1. A bidirectional Zener diode comprising: asubstrate; a first conductivity type base region formed at a frontsurface portion of the substrate; a second conductivity type firstimpurity region formed at the base region; a second conductivity typesecond impurity region formed at the base region away from the firstimpurity region; an insulating layer formed on a front surface of thesubstrate; a first electrode film formed on the insulating layer andelectrically connected to the first impurity region; a second electrodefilm formed on the insulating layer and electrically connected to thesecond impurity region; and a first region formed on the insulatinglayer, the first region being sandwiched between the first electrodefilm and the second electrode film, and the first region including aportion having an aspect ratio of 1 or larger.
 2. The bidirectionalZener diode according to claim 1, wherein the first electrode filmincludes a first pad portion disposed away from the first impurityregion in a direction along the front surface of the substrate and afirst wiring portion that extends from the first pad portion to a regionon the first impurity region, and the first wiring portion has a largestfirst width in a connection portion connected to the first pad portion.3. The bidirectional Zener diode according to claim 2, wherein the firstwiring portion is formed in a tapered shape so as to become graduallythinner toward a tip end portion of the first wiring portion from theconnection portion connected to the first pad portion.
 4. Thebidirectional Zener diode according to claim 3, wherein the largestfirst width in the connection portion connected to the first pad portionof the first wiring portion is twice or more a width of the tip endportion of the first wiring portion.
 5. The bidirectional Zener diodeaccording to claim 2, wherein the second electrode film includes asecond pad portion disposed away from the second impurity region in adirection along the front surface of the substrate and a second wiringportion that extends from the second pad portion to a region on thesecond impurity region, and the second wiring portion has a largestsecond width in a connection portion connected to the second padportion.
 6. The bidirectional Zener diode according to claim 5, whereinthe second wiring portion is formed in a tapered shape so as to becomegradually thinner toward a tip end portion of the second wiring portionfrom the connection portion connected to the second pad portion.
 7. Thebidirectional Zener diode according to claim 6, wherein the largestsecond width in the connection portion connected to the second padportion of the second wiring portion is twice or more a width of the tipend portion of the second wiring portion.
 8. The bidirectional Zenerdiode according to claim 1, wherein a thickness of the first electrodefilm and a thickness of the second electrode film are each 3 μm to 5 μm,and a distance between the first electrode film and the second electrodefilm in the portion having the aspect ratio of the first region is 0.5μm to 5 μm.
 9. The bidirectional Zener diode according to claim 1,wherein the first electrode film and the second electrode film are eachmade of AlCu.
 10. The bidirectional Zener diode according to claim 1,wherein the insulating layer has a first contact hole that exposes thefirst impurity region, and the first electrode film is connected to thefirst impurity region through the first contact hole, and the insulatinglayer includes a first portion that has a first thickness and that formsthe first contact hole and a second portion that surrounds the firstportion and that has a second thickness larger than the first thickness.11. The bidirectional Zener diode according to claim 10, wherein theinsulating layer includes a third portion that is formed between thefirst portion and the second portion and that has a third thicknesssmaller than the first thickness.
 12. The bidirectional Zener diodeaccording to claim 10, wherein the insulating layer has a second contacthole that exposes the second impurity region, and the second electrodefilm is connected to the second impurity region through the secondcontact hole, and the insulating layer includes a fourth portion thathas a fourth thickness and that forms the second contact hole and afifth portion that surrounds the fourth portion and that has a fifththickness larger than the fourth thickness.
 13. The bidirectional Zenerdiode according to claim 12, wherein the insulating layer includes asixth portion that is formed between the fourth portion and the fifthportion and that has a sixth thickness smaller than the fourththickness.
 14. The bidirectional Zener diode according to claim 1,wherein a plurality of the first impurity regions and a plurality of thesecond impurity regions are alternately arrayed along a predeterminedarray direction.
 15. The bidirectional Zener diode according to claim 1,further comprising: a first external electrode that is connected to thefirst electrode film and that has a front surface including a pluralityof first convex portions partitioned by a first groove; and a secondexternal electrode that is connected to the second electrode film andthat has a front surface including a plurality of second convex portionspartitioned by a second groove.
 16. The bidirectional Zener diodeaccording to claim 15, wherein the plurality of first convex portionsand the plurality of second convex portions are each arrayed in astaggered manner.
 17. A method for manufacturing a bidirectional Zenerdiode, the method comprising: a step of implanting a second conductivitytype impurity into a first conductivity type base region formed at afront surface portion of a substrate and then forming a first impurityregion and a second impurity region away from each other by applyingheat treatment; a step of forming an insulating layer on a front surfaceof the substrate; a step of forming an electrode film on the insulatinglayer so as to be electrically connected to the first impurity regionand to the second impurity region; and a step of applying dry etching tothe electrode film and hence forming the electrode film into anelectrode pattern that includes a first electrode film electricallyconnected to the first impurity region and a second electrode filmelectrically connected to the second impurity region, wherein theelectrode pattern has a first region that is sandwiched between thefirst electrode film and the second electrode film and that includes aportion having an aspect ratio of 1 or larger.